1. Field of the Invention
The invention relates to a DC-to-DC converter control circuit having fast response characteristics against a sudden change in load, and a DC-to-DC converter control method using the same, and in particular, to a DC-to-DC converter control circuit aiming at compatibility with low ripple voltage characteristics, and a DC-to-DC converter control method using the same.
2. Description of the Related Art
FIG. 7 shows a current control type DC-to-DC converter circuit. It has a configuration wherein switching control by a synchronous rectification method is executed by a main transistor FET1 and a synchronous transistor FET2, interconnecting an input voltage VIN and the ground potential.
With a DC-to-DC converter control circuit 100, input terminals CS1, and FB1, connected with respective ends of a sense resistor RS, are connected to a noninverting input terminal, and an inverting input terminal of a level converter A100, respectively, and when a coil current flowing through a choke coil L1 is inputted thereto as voltage signals, a difference signal thereof is amplified to be outputted in a necessary voltage range (a voltage signal VP). Further, a voltage difference between an output voltage VOUT inputted from the input terminal FB1 connected to an output terminal VOUT, and a reference voltage E1 undergoes error amplification by an error amplifier E100 (an error amplification signal VC). The voltage signal VP, and the error amplification signal VC are inputted to a noninverting input terminal, and an inverting input terminal of a voltage comparator CMP2, respectively. A flip-flop circuit FF2 as set by a high-level signal from an oscillator C1 causes the main transistor FET1 to be turned into conductive state via an output terminal DH. As a result, the coil current increases, and an output of the voltage comparator CMP2 is inverted to a high-level, thereby resetting the flip-flop circuit FF2. This causes the synchronous transistor FET2 to be turned into conductive state via an output terminal DL. There is adopted a frequency fixing method whereby such an operation as above is repeated at the cycle of the oscillator O1.
When the main transistor FET1 is in conductive state, the coil current flows from the input voltage VIN toward the output terminal VOUT via the choke coil L1, and increases with time. Since the level converter A100 amplifies the coil current converted into voltage by the sense resistor RS, the voltage signal VP outputted from the level converter A100 increases in magnitude as the coil current increases. The voltage comparator CMP2 resets the flip-flop circuit FF2 upon the voltage signal VP becoming larger in magnitude than the error amplification signal VC. This will turn the main transistor FET1 into non-conductive state while turning the synchronous transistor FET2 into conductive state.
With a DC-to-DC converter control circuit shown in FIG. 8, it is possible to aim at fast response against a sudden change in load. This is a control by the so-called comparator control method. Herein, resistance ESR connected in series to a smoothing capacitor C1 indicates an equivalent series-connected resistance ESR included in the smoothing capacitor C1.
An output voltage VOUT is connected to an input terminal FB1 of a DC-to-DC converter control circuit 200 to undergo resistance type voltage division, thereby being inputted to an inverting input terminal of a voltage comparator CMP1. A reference voltage E1 is connected to a noninverting input terminal of the voltage comparator CMP1. An output terminal of the voltage comparator CMP1 is connected to a set terminal of a flip-flop circuit FF1. The flip-flop circuit FF1 adopts a fixed pulse width method whereby a one shot high-level signal is outputted from a noninverting output terminal Q against setting input. The noninverting output terminal Q, an inverting output terminal /Q of the flip-flop circuit FF1 are connected to a main transistor FET1, and a synchronous transistor FET2 via output terminals DH, DL, respectively.
When the output voltage VOUT drops below the reference voltage E1, the voltage comparator CMP1 outputs a high-level signal to thereby set the flip-flop circuit FF1. In response to setting of the flip-flop circuit FF1, the main transistor FET1 is turned into conductive state, and a current is supplied from an input voltage VIN to a load via a choke coil L1, whereupon the output voltage VOUT of the DC-to-DC converter increases. With the elapse of predetermined time, the flip-flop circuit FF1 is reset, and the synchronous transistor FET2 is turned into conductive state. Energy stored in the choke coil L1 is supplied to the load via the synchronous transistor FET2, but a current flowing through the choke coil L1 gradually decreases as the energy is discharged, and the output voltage VOUT of the DC-to-DC converter also gradually decreases. When the output voltage VOUT drops below the reference voltage E1, the voltage comparator CMP1 outputs a high-level signal again to thereby set the flip-flop circuit FF1. The operation described as above is repeated.
Patent Documents 1 to 3, concerning the technologies related to the above, have since been disclosed.
[Patent Document 1]
Japanese unexamined patent publication No. H10(1998)-225105
[Patent Document 2]
Japanese unexamined patent publication No. 2000-287439
[Patent Document 3]
Japanese unexamined patent publication No. 2000-32744